1. Field of the Invention
This invention relates to a memory refresh circuit. More specifically, this invention relates to a memory refresh circuit for operating a fixed-timing circuit over a substantial range of clock frequencies.
2. Description of the Relevant Art
Due to the complex nature of VLSI circuit designs, including microprocessor circuit designs, validation of the designs includes debugging of circuitry on several levels. For example, a processor design may be tested using silicon parts operating in a motherboard at full speed. The same processor design may also be tested using an emulator operating in a motherboard at low speed.
Silicon parts operate in the motherboard at an operating speed in the range of tens of megahertz. In contrast, the emulator operates in the motherboard at an operating speed in the range of hundreds of kilohertz. Accordingly, the operating speed of the motherboard varies at a ratio of approximately 100 to 1 in this example. Although separate motherboards may be utilized for different testing levels including a high-speed motherboard and a low-speed motherboard, advantages are gained by using the same motherboard for all testing and validation. In particular, usage of a single motherboard substantially reduces the number of variables or differences in operating conditions. Furthermore, usage of a single motherboard is convenient. If the same motherboard is used for both the high speed and low speed applications, the motherboard must have an operating range at least from the hundreds of kilohertz to the tens of megahertz.
Several problems are raised by attempting to operate a motherboard over this wide range of frequencies. For example, the wide range of operating frequencies raises problems with regard to dynamic random access memory (DRAM) refresh. FIG. 1 is a schematic block diagram which illustrates a conventional refresh circuit 100. The conventional refresh circuit 100 includes a refresh clock generator circuit 110, a refresh flip-flop 112, a dynamic random access memory (DRAM) controller 116 and a dynamic random access memory (DRAM) 118. The refresh clock generator circuit 110 generates a rising edge of a periodic signal at a specified rate, for example 15 .mu.s. A typical DRAM, such as DRAM 118, has 256 rows that are refreshed in 4 milliseconds (ms) so that the average refresh rate is 15 microseconds (.mu.s). Accordingly, the typical refresh clock generator circuit 110 generates a refresh signal every 15 .mu.s. The refresh signal sets the flip-flop 112. A refresh cycle takes place when a refresh circuit 100 gains control of the DRAM 118. Once the refresh cycle is completed, the flip-flop 112 is cleared. The underlying implication is that the DRAM 118 must become available to the refresh circuit 100 for refresh before another 15 .mu.s time slice expires. Thus, the typical refresh circuit 100 is synchronized with the typical DRAM 118 on the basis that the average refresh rate of the DRAM 118 is similar to the refresh rate generated by the refresh clock generator circuit 110. No circuits or memory are generally used to enforce this synchronization.
The refresh timing requirement of a DRAM remains the same regardless of the clock rate and operating speed of a processor 106. The DRAM continues to require a designated refresh time. Thus at very low-speed operating rates, such as the rates used in emulation, the very slow access to DRAM 118 of the processor 106 may extend for several refresh cycles. For example, if the processor 106 access is extended to 100 .mu.s, then the refresh time of the DRAM 118 is exceeded. The refresh generator generates six refresh cycles of which only one results in a refresh cycle to the DRAM 118. Five refresh cycles are missed. So much time has transpired between refresh signals to the DRAM 118 that a few refresh cycles are skipped. Under these circumstances, the refresh specification for the DRAM 118 will eventually be violated.
What is needed is a circuit that is functionally the same while operating at high frequency and at low frequency. What is needed is a timing refresh circuit that refreshes a DRAM in a functionally equivalent manner, whether the timing refresh circuit is operated at a high frequency or a low frequency.